Series:

Frontiers in Electronic Testing

2 primary works • 3 total works

Book 34

Cover of Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits

The 2nd edition of defect oriented testing has been extensively updated. New chapters on Functional, Parametric Defect Models and Inductive fault Analysis and Yield Engineering have been added to provide a link between defect sources and yield. The chapter on RAM testing has been updated with focus on parametric and SRAM stability testing. Similarly, newer material has been incorporated in digital fault modeling and analog testing chapters. The strength of Defect Oriented Testing for nano-Metric CMOS VLSIs lies in its industrial relevance.

Book 40

Cover of CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies

The monograph will be dedicated to SRAM (memory) design and test issues in nano-scaled technologies by adapting the cell design and chip design considerations to the growing process variations with associated test issues. Purpose: provide process-aware solutions for SRAM design and test challenges.

v. 10

Cover of Defect Oriented Testing for CMOS Analog and Digital Circuits
Defect-oriented testing methods have come a long way from a mere interesting academic exercise to a hard industrial reality, and many factors have contributed to their industrial acceptance. Traditional approaches of testing modern integrated circuits (ICs) have been found to be inadequate in terms of quality and economics of test. In a globally competitive semiconductor market-place, overall product quality and economics have become very important objectives. In addition, electronic systems are becoming increasingly complex, and demand components of the highest possible quality. Testing in general, and defect-oriented testing in particular, help in realizing these objectives. Providing a detailed overview of the subject, this book is intended for design and test professionals as well as researchers and students working in the field.