The Springer International Series in Engineering and Computer Science
2 primary works
Book 430
Design of Modulators for Oversampled Converters
by Feng Wang and Ramesh Harjani
Published 30 November 1997
Oversampled A/D converters have become very popular in recent years. Some of their advantages include relaxed requirements for anti-alias filters, relaxed requirements for component matching, high resolution and compatibility with digital VLSI technology. There is a significant amount of literature discussing the principle, theory and implementation of various oversampled converters. Such converters are likely to continue to proliferate in the foreseeable future. Additionally, more recently there has been great interest in low voltage and low power circuit design. New design techniques have been proposed for both the digital domain and the analog domain. Both trends point to the importance of the low-power design of oversampled A/D converters.
Unfortunately, there has been no systematic study of the optimal design of modulators for oversampled converters. Design has generally focused on new architectures with little attention being paid to optimization.
The goal of Design of Modulators for Oversampled Converters is to develop a methodology for the optimal design of modulators in oversampled converters. The primary focus of the presentation is on minimizing power consumption and understanding and limiting the nonlinearities that result in such converters.
Design of Modulators for Oversampled Converters offers a quantitative justification for the various design tradeoffs and serves as a guide for designing low-power highly linear oversampled converters. Design of Modulators for Oversampled Converters will serve as a valuable guide for circuit design practitioners, university researchers and graduate students who are interested in this fast-moving area.
Unfortunately, there has been no systematic study of the optimal design of modulators for oversampled converters. Design has generally focused on new architectures with little attention being paid to optimization.
The goal of Design of Modulators for Oversampled Converters is to develop a methodology for the optimal design of modulators in oversampled converters. The primary focus of the presentation is on minimizing power consumption and understanding and limiting the nonlinearities that result in such converters.
Design of Modulators for Oversampled Converters offers a quantitative justification for the various design tradeoffs and serves as a guide for designing low-power highly linear oversampled converters. Design of Modulators for Oversampled Converters will serve as a valuable guide for circuit design practitioners, university researchers and graduate students who are interested in this fast-moving area.
Book 708
Design of High-Performance CMOS Voltage-Controlled Oscillators
by Liang Dai and Ramesh Harjani
Published 31 October 2002
Design of High-Performance CMOS Voltage-Controlled Oscillators presents a phase noise modeling framework for CMOS ring oscillators. The analysis considers both linear and nonlinear operation. It indicates that fast rail-to-rail switching has to be achieved to minimize phase noise. Additionally, in conventional design the flicker noise in the bias circuit can potentially dominate the phase noise at low offset frequencies. Therefore, for narrow bandwidth PLLs, noise up conversion for the bias circuits should be minimized. We define the effective Q factor (Qeff) for ring oscillators and predict its increase for CMOS processes with smaller feature sizes. Our phase noise analysis is validated via simulation and measurement results.
The digital switching noise coupled through the power supply and substrate is usually the dominant source of clock jitter. Improving the supply and substrate noise immunity of a PLL is a challenging job in hostile environments such as a microprocessor chip where millions of digital gates are present.
The digital switching noise coupled through the power supply and substrate is usually the dominant source of clock jitter. Improving the supply and substrate noise immunity of a PLL is a challenging job in hostile environments such as a microprocessor chip where millions of digital gates are present.