Series:

The Springer International Series in Engineering and Computer Science

8 primary works

Book 2

Cover of Logic Minimization Algorithms for VLSI Synthesis
The roots of the project which culminates with the writing of this book can be traced to the work on logic synthesis started in 1979 at the IBM Watson Research Center and at University of California, Berkeley. During the preliminary phases of these projects, the impor tance of logic minimization for the synthesis of area and performance effective circuits clearly emerged. In 1980, Richard Newton stirred our interest by pointing out new heuristic algorithms for two-level logic minimization and the potential for improving upon existing approaches. In the summer of 1981, the authors organized and participated in a seminar on logic manipulation at IBM Research. One of the goals of the seminar was to study the literature on logic minimization and to look at heuristic algorithms from a fundamental and comparative point of view. The fruits of this investigation were surprisingly abundant: it was apparent from an initial implementation of recursive logic minimiza tion (ESPRESSO-I) that, if we merged our new results into a two-level minimization program, an important step forward in automatic logic synthesis could result. ESPRESSO-II was born and an APL implemen tation was created in the summer of 1982. The results of preliminary tests on a fairly large set of industrial examples were good enough to justify the publication of our algorithms. It is hoped that the strength and speed of our minimizer warrant its Italian name, which denotes both express delivery and a specially-brewed black coffee.

Book 20

Cover of Relaxation Techniques for the Simulation of VLSI Circuits
Circuit simulation has been a topic of great interest to the integrated circuit design community for many years. It is a difficult, and interesting, problem be cause circuit simulators are very heavily used, consuming thousands of computer hours every year, and therefore the algorithms must be very efficient. In addi tion, circuit simulators are heavily relied upon, with millions of dollars being gambled on their accuracy, and therefore the algorithms must be very robust. At the University of California, Berkeley, a great deal of research has been devoted to the study of both the numerical properties and the efficient imple mentation of circuit simulation algorithms. Research efforts have led to several programs, starting with CANCER in the 1960's and the enormously successful SPICE program in the early 1970's, to MOTIS-C, SPLICE, and RELAX in the late 1970's, and finally to SPLICE2 and RELAX2 in the 1980's. Our primary goal in writing this book was to present some of the results of our current research on the application of relaxation algorithms to circuit simu lation. As we began, we realized that a large body of mathematical and exper imental results had been amassed over the past twenty years by graduate students, professors, and industry researchers working on circuit simulation. It became a secondary goal to try to find an organization of this mass of material that was mathematically rigorous, had practical relevance, and still retained the natural intuitive simplicity of the circuit simulation subject.

Book 94

Cover of Steady-State Methods for Simulating Analog and Microwave Circuits
The motivation for starting the work described in this book was the interest that Hewlett-Packard's microwave circuit designers had in simulation techniques that could tackle the problem of finding steady­ state solutions for nonlinear circuits, particularly circuits containing distributed elements such as transmission lines. Examining the problem of computing steady-state solutions in this context has led to a collection of novel numerical algorithms which we have gathered, along with some background material, into this book. Although we wished to appeal to as broad an audience as possible, to treat the subject in depth required maintaining a narrow focus. Our compromise was to assume that the reader is familiar with basic numerical methods, such as might be found in [dahlquist74] or [vlach83], but not assume any specialized knowledge of methods for steady-state problems. Although we focus on algorithms for computing steady-state solutions of analog and microwave circuits, the methods herein are general in nature and may find use in other disciplines. A number of new algorithms are presented, the contributions primarily centering around new approaches to harmonic balance and mixed frequency-time methods. These methods are described, along with appropriate background material, in what we hope is a reasonably satisfying blend of theory, practice, and results. The theory is given so that the algorithms can be fully understood and their correctness established.

Book 139

Cover of Integrating Functional and Temporal Domains in Logic Design
This book is an extension of one author's doctoral thesis on the false path problem. The work was begun with the idea of systematizing the various solutions to the false path problem that had been proposed in the literature, with a view to determining the computational expense of each versus the gain in accuracy. However, it became clear that some of the proposed approaches in the literature were wrong in that they under estimated the critical delay of some circuits under reasonable conditions. Further, some other approaches were vague and so of questionable accu racy. The focus of the research therefore shifted to establishing a theory (the viability theory) and algorithms which could be guaranteed correct, and then using this theory to justify (or not) existing approaches. Our quest was successful enough to justify presenting the full details in a book. After it was discovered that some existing approaches were wrong, it became apparent that the root of the difficulties lay in the attempts to balance computational efficiency and accuracy by separating the tempo ral and logical (or functional) behaviour of combinational circuits. This separation is the fruit of several unstated assumptions; first, that one can ignore the logical relationships of wires in a network when considering timing behaviour, and, second, that one can ignore timing considerations when attempting to discover the values of wires in a circuit.

Book 232

Cover of Algorithms for Synthesis and Testing of Asynchronous Circuits
Since the second half of the 1980s asynchronous circuits have been the subject of a great deal of research following a period of relative oblivion. The lack of interest in asynchronous techniques was motivated by the progressive shift towards synchronous design techniques that had much more structure and were much easier to verify and synthesize. System design requirements made it impossible to eliminate totally the use of asynchronous circuits. Given the objective difficulty encountered by designers, the asynchronous components of electronic systems such as interfaces became a serious bottleneck in the design process. The use of new models and some theoretical breakthroughs made it possible to develop asynchronous design techniques that were reliable and effective. This book describes a variety of mathematical models and of algorithms that form the backbone and the body of a new design methodology for asyn­ chronous design. The book is intended for asynchronous hardware designers, for computer-aided tool experts, and for digital designers interested in ex­ ploring the possibility of designing asynchronous circuits. It requires a solid mathematical background in discrete event systems and algorithms. While the book has not been written as a textbook, nevertheless it could be used as a reference book in an advanced course in logic synthesis or asynchronous design.

Book 270

Cover of Timed Boolean Functions
Timing research in high performance VLSI systems has advanced at a steady pace over the last few years, while tools, especially theoretical mechanisms, lag behind. Much present timing research relies heavily on timing diagrams, which, although intuitive, are inadequate for analysis of large designs with many parameters. Further, timing diagrams offer only approximations, not exact solutions, to many timing problems and provide little insight in the cases where temporal properties of a design interact intricately with the design's logical functionalities. This book presents a methodology for timing research which facilitates analy sis and design of circuits and systems in a unified temporal and logical domain. In the first part, we introduce an algebraic representation formalism, Timed Boolean Functions (TBF's), which integrates both logical and timing informa tion of digital circuits and systems into a single formalism. We also give a canonical form, TBF BDD's, for them, which can be used for efficient ma nipulation. In the second part, we apply Timed Boolean Functions to three problems in timing research, for which exact solutions are obtained for the first time: 1. computing the exact delays of combinational circuits and the minimum cycle times of finite state machines, 2. analysis and synthesis of wavepipelining circuits, a high speed architecture for which precise timing relations between signals are essential for correct operations, 3. verification of circuit and system performance and coverage of delay faults by testing.

Book 324

Cover of Logic Synthesis for Field-Programmable Gate Arrays
Short turnaround has become critical in the design of electronic systems. Software- programmable components such as microprocessors and digital signal processors have been used extensively in such systems since they allow rapid design revisions. However, the inherent performance limitations of software-programmable systems mean that they are inadequate for high-performance designs. Designers thus turned to gate arrays as a solution. User-programmable gate arrays (field-programmable gate arrays, FPGAs) have recently emerged and are changing the way electronic systems are designed and implemented. The growing complexity of the logic circuits that can be packed onto an FPGA chip means that it has become important to have automatic synthesis tools that implement logic functions on these architectures. Logic Synthesis for Field-Programmable Gate Arrays describes logic synthesis for both look-up table (LUT) and multiplexor-based architectures, with a balanced presentation of existing techniques together with algorithms and the system developed by the authors.
Audience: A useful reference for VLSI designers, developers of computer-aided design tools, and anyone involved in or with FPGAs.

Book 585

Cover of Function/Architecture Optimization and Co-Design of Embedded Systems
Function Architecture Co-Design is a new paradigm for the design and implementation of embedded systems. Function/Architecture Optimization and Co-Design of Embedded Systems presents the authors' work in developing a function/architecture optimization and co-design formal methodology and framework for control-dominated embedded systems. The approach incorporates both data flow and control optimizations performed on a suitable novel intermediate design task representation. The aim is not only to enhance productivity of the designer and system developer, but also to improve quality of the final synthesis outcome.
Function/Architecture Optimization and Co-Design of Embedded Systems discusses the proposed function/architecture co-design methodology, focusing on design representation, optimization, validation, and synthesis. Throughout the text, the difference between behavior specification and implementation is emphasized. The current need in co-design to move from synthesis-based technology to compiler-based technology is pointed out. The authors describe and show how performing data flow and control optimizations at the high abstraction level can lead to significant size and performance improvements in both the synthesized hardware and software. The work builds on bodies of research in the silicon and software compilation domains. The aforementioned techniques are specialized to the embedded systems domain. It is recognized that guided optimization can be applied on the internal design representation, no matter what the abstraction level, and need not be restricted to the final stages of software assembly code generation, or hardware synthesis.
Function/Architecture Optimization and Co-Design of Embedded Systems will be of primary interest to researchers, developers, and professionals in the field of embedded systems design.