As the supply voltage of circuits decreases to reduce power consumption, analog designs require more physical, accurate, and continuous compact MOS (metal-oxide semiconductor) models. The analog design cycle involves architecture and circuit topology development, current and width/length sizing selection for each MOS transistor, and extensive verification to ensure a high-performance, robust, and high-yielding design for volume production. "Optimizing Analog CMOS Design" presents a unique methodology for optimizing analog design, especially at low supply voltages.
- ISBN10 0470863951
- ISBN13 9780470863954
- Publish Date 12 March 2010 (first published 12 September 2006)
- Publish Status Cancelled
- Out of Print 17 November 2005
- Publish Country GB
- Publisher John Wiley and Sons Ltd
- Imprint John Wiley & Sons Ltd
- Format Hardcover
- Pages 320
- Language English