VHDL: A logic synthesis approach

by D. Naylor and S Jones

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Book cover for VHDL: A logic synthesis approach

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This book is structured in a practical, example-driven, manner. The use of VHDL for constructing logic synthesisers is one of the aims of the book; the second is the application of the tools to the design process. Worked examples, questions and answers are provided together with do and don'ts of good practice. An appendix on logic design the source code are available free of charge over the Internet.
  • ISBN13 9780412616501
  • Publish Date 31 July 1997
  • Publish Status Active
  • Publish Country GB
  • Publisher Taylor & Francis Ltd
  • Imprint Chapman and Hall
  • Edition 1997 ed.
  • Format Hardcover
  • Pages 340
  • Language English