For introductory-level courses in Verilog Hardware Description Language. Written by the co-developer of the Verilog Implicit To One hot (VITO) preprocessor, this text introduces the industry standard Verilog Hardware Description Language as a new way to explore enduring concepts in digital and computer design, such as pipelining. It shows how Verilog simulation is a tool for uncovering bugs prior to hardware fabrication, and how Verilog synthesis is a tool for automatically converting source code into hardware. Ideal for designers new to Verilog, it features a consistent design framework using ASM charts, and contains many realistic, practical examples.
- ISBN10 0136392539
- ISBN13 9780136392538
- Publish Date 2 September 1998
- Publish Status Out of Print
- Out of Print 15 March 2021
- Publish Country US
- Imprint Prentice Hall
- Format Hardcover
- Pages 640
- Language English