For senior/graduate-level courses in Advanced Digital Design and Advanced Digital Logic in departments of electrical engineering, computer engineering, and computer science.
Intended to teach a synthesis-based approach to design using a hardware description language (i.e., VHDL), this text focuses on the synthesis process in how to translate VHDL descriptions into gate level logic. It teaches the VHDL language in detail, describes modeling at three different levels of abstraction (algorithmic, data flow, and gate level), and explains the ASIC Design Process. Illustrations of synthesis with standard cell libraries and FPGAs are given using Synopsys and Xilinx tools.
- ISBN10 0130216704
- ISBN13 9780130216700
- Publish Date 12 April 2000 (first published 1 June 1993)
- Publish Status Out of Print
- Out of Print 15 March 2021
- Publish Country US
- Imprint Prentice Hall
- Edition 2nd edition
- Format Paperback
- Pages 651
- Language English