xv From the Old to the New xvii Acknowledgments xxi 1 Verilog - A Tutorial Introduction 1 Getting Started 2 A Structural Description 2 Simulating the binaryToESeg Driver 4 Creating Ports For the Module 7 Creating a Testbench For a Module 8 11 Behavioral Modeling of Combinational Circuits Procedural Models 12 Rules for Synthesizing Combinational Circuits 13 14 Procedural Modeling of Clocked Sequential Circuits Modeling Finite State Machines 15 Rules for Synthesizing Sequential Systems 18 Non-Blocking Assignment ("
- ISBN13 9781475775891
- Publish Date 15 February 2014 (first published 1 January 2002)
- Publish Status Active
- Publish Country US
- Imprint Springer-Verlag New York Inc.
- Edition 5th ed. 2002. Softcover reprint of the original 5th ed. 2002
- Format Paperback
- Pages 382
- Language English