XV From the Old to the New xvii Acknowledgments xx| Verilog A Tutorial Introduction Getting Started 2 A Structural Description 2 Simulating the binaryToESeg Driver 4 Creating Ports For the Module 7 Creating a Testbench For a Module 8 Behavioral Modeling of Combinational Circuits 11 Procedural Models 12 Rules for Synthesizing Combinational Circuits 13 Procedural Modeling of Clocked Sequential Circuits 14 Modeling Finite State Machines 15 Rules for Synthesizing Sequential Systems 18 Non-Blocking Assignment ("
- ISBN13 9780387849300
- Publish Date 8 October 2008
- Publish Status Active
- Publish Country US
- Imprint Springer-Verlag New York Inc.
- Edition 5th ed. 2002
- Format Paperback
- Pages 386
- Language English