Wafer-Level Testing and Test During Burn-In for Integrated Circuits (Artech House Integrated Microsystems)

by Sudarshan Bahukudumbi and Krishnendu Chakrabarty

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Book cover for Wafer-Level Testing and Test During Burn-In for Integrated Circuits

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Wafer-level testing refers to a critical process of subjecting integrated circuits and semiconductor devices to electrical testing while they are still in wafer form. Burn-in is a temperature/bias reliability stress test used in detecting and screening out potential early life device failures. This hands-on resource provides a comprehensive analysis of these methods, showing how wafer-level testing during burn-in (WLTBI) helps lower product cost in semiconductor manufacturing. Engineers learn how to implement the testing of integrated circuits at the wafer-level under various resource constraints. Moreover, this unique book helps practitioners address the issue of enabling next generation products with previous generation testers. Practitioners also find expert insights on current industry trends in WLTBI test solutions.
  • ISBN10 1596939907
  • ISBN13 9781596939905
  • Publish Date 1 February 2010
  • Publish Status Active
  • Publish Country US
  • Imprint Artech House Publishers
  • Format eBook
  • Pages 210
  • Language English