Richard Munden demonstrates how to create and use simulation models for verifying ASIC and FPGA designs and board-level designs that use off-the-shelf digital components. Based on the VHDL/VITAL standard, these models include timing constraints and propagation delays that are required for accurate verification of today's digital designs.
ASIC and FPGA Verification: A Guide to Component Modeling expertly illustrates how ASICs and FPGAs can be verified in the larger context of a board or a system. It is a valuable resource for any designer who simulates multi-chip digital designs.
- ISBN10 6611008284
- ISBN13 9786611008284
- Publish Date 1 January 2005 (first published 1 January 2004)
- Publish Status Active
- Out of Print 22 June 2011
- Publish Country US
- Imprint Elsevier Science & Technology
- Format eBook
- Pages 336
- Language English