Wiley Series in Parallel Computing
1 total work
Examines the theory and design of self-timed systems. The logical design of self-timed circuits (STCs) provides a focal point for, on the one hand, those interested in formal models of parallel computation and, on the other, hardware designers. The approach taken by the authors is to address general issues concerning the very nature of concurrency, as well as to demonstrate the particular features of asynchronous design. The book presents formal models of the specification and verification of parallel processes and describes methods for self-timed circuit synthesis and analysis. It is augmented by a demonstration-version of a CAD system called FORCAGE which consists of subsystems of behavior verification, self-timed circuit analysis and synthesis. The system can be run on a PC.