The "SystemVerilog for Verification" book is a follow-on to the "SystemVerilog for Design" book, published earlier this year. The book will introduce the reader to the advanced testbench, verification and programming features of the Accellera SystemVerilog 3.1a standard, focusing on how these constructs can be used to set up effective verification methodologies. Readers should have a working knowledge of the Verilog HDL and preferably have read the "SystemVerilog for Design" book. Familiarity with other verification languages, Object-Oriented programming, constrained-random data generation and assertion languages would be helpful, although these topics will be covered in detail. Other topics to be covered include: Advanced programming features, including dynamic and associative arrays; Multiple processes, synchronization, communication and process control; Functional coverage. The book will contain appendices that discuss the new programming interfaces that are included in SystemVerilog 3.1a.
- ISBN10 0387255710
- ISBN13 9780387255712
- Publish Date 1 December 2007
- Publish Status Active
- Out of Print 22 May 2007
- Publish Country US
- Imprint Springer-Verlag New York Inc.
- Format Hardcover
- Pages 400
- Language English