Verilog Styles for Synthesis of Digital Systems

by David R Smith and Paul D. Franzon

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For senior/graduate-level courses in Digital Hardware Design/Verilog.

This text is designed specifically to make the cutting-edge techniques of digital hardware design more accessible to students-e.g., synthesis from high-level specifications, and field programmable gate arrays (FPGA) for many applications. The text uses a simpler language (Verilog) and standardizes the methodology to the point where seniors and first-year graduates can get medium complex designs through to gate-level simulation in a single semester.

  • ISBN10 0201618605
  • ISBN13 9780201618600
  • Publish Date 10 October 2000
  • Publish Status Out of Print
  • Out of Print 15 March 2021
  • Publish Country US
  • Imprint Pearson
  • Format Paperback
  • Pages 336
  • Language English