Direct Transistor-Level Layout for Digital Blocks (Praxis Der Bauwirtschaft)

by Prakash Gopalakrishnan, Rob A. Rutenbar, and Gopalakrishnan Prakash

0 ratings • 0 reviews • 0 shelved
Book cover for Direct Transistor-Level Layout for Digital Blocks

Bookhype may earn a small commission from qualifying purchases. Full disclosure.

Cell-based design methodologies have dominated layout generation of digital circuits. Unfortunately, the growing demands for transparent process portability, increased performance, and low-level device sizing for timing/power are poorly handled in a fixed cell library.
Direct Transistor-Level Layout For Digital Blocks proposes a direct transistor-level layout approach for small blocks of custom digital logic as an alternative that better accommodates demands for device-level flexibility. This approach captures essential shape-level optimizations, yet scales easily to netlists with thousands of devices, and incorporates timing optimization during layout. The key idea is early identification of essential diffusion-merged MOS device groups, and their...Read more
  • ISBN10 1280147679
  • ISBN13 9781280147678
  • Publish Date 1 January 2005 (first published 17 June 2004)
  • Publish Status Active
  • Out of Print 25 March 2015
  • Publish Country US
  • Imprint Springer Us
  • Pages 125
  • Language English