This book describes innovative techniques to address the testing needs of 3D stacked integrated circuits (ICs) that utilize through-silicon-vias (TSVs) as vertical interconnects. The authors identify the key challenges facing 3D IC testing and present results that have emerged from cutting-edge research in this domain. Coverage includes topics ranging from die-level wrappers, self-test circuits, and TSV probing to test-architecture design, test scheduling, and optimization. Readers will benefit from an in-depth look at test-technology solutions that are needed to make 3D ICs a reality and commercially viable.
- ISBN13 9783319023779
- Publish Date 2 December 2013 (first published 30 November 2013)
- Publish Status Active
- Publish Country CH
- Imprint Springer International Publishing AG
- Edition 2014 ed.
- Format Hardcover
- Pages 245
- Language English