This book is intended as an innovative overview of current formal verification methods, combined with an in-depth analysis of some advanced techniques to improve the scalability of these methods, and close the gap between design and verification in computer-aided design. Formal Verification: Scalable Hardware Verification with Symbolic Simulation explains current formal verification methods and provides an in-depth analysis of some advanced techniques to improve the scalability of these methods and close the gap between design and verification in computer-aided design. It provides the theoretical background required to present such methods and advanced techniques, i.e. Boolean function representations, models of sequential networks and, in particular, some novel algorithms to expose the disjoint support decompositions of Boolean functions, used in one of the scalable approaches.
- ISBN10 0387505059
- ISBN13 9780387505053
- Publish Date 17 March 2011 (first published 21 December 2005)
- Publish Status Withdrawn
- Out of Print 18 October 2014
- Publish Country DE
- Imprint Springer
- Edition New ed.
- Format Paperback (US Trade)
- Pages 301
- Language English