SystemVerilog is a rich set of extensions to the IEEE 1364-2001 Verilog Hardware Description Language (Verilog HDL). These extensions address two major aspects of HDL based design. First, modeling very large designs with concise, accurate, and intuitive code. Second, writing high-level test programs to efficiently and effectively verify these large designs. This book, "SystemVerilog for Design", addresses the first aspect of the SystemVerilog extensions to Verilog. Important modeling features are presented, such as two-state data types, enumerated types, user-defined types, structures, unions, and interfaces. Emphasis is placed on the proper usage of these enhancements for simulation and synthesis. A companion to this book, "SystemVerilog for Verification", covers the second aspect of SystemVerilog.
- ISBN10 6610619298
- ISBN13 9786610619290
- Publish Date 1 January 2006 (first published 30 June 2003)
- Publish Status Active
- Out of Print 9 February 2012
- Publish Country US
- Imprint Springer
- Format eBook
- Pages 437
- Language English