Synthesizable VHDL Design for FPGAs

by Eduardo Bezerra and Djones Vinicius Lettnin

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The methodology described in this book is the result of many years of research experience in the field of synthesizable VHDL design targeting FPGA based platforms. VHDL was first conceived as a documentation language for ASIC designs. Afterwards, the language was used for the behavioral simulation of ASICs, and also as a design input for synthesis tools. VHDL is a rich language, but just a small subset of it can be used to write synthesizable code, from which a physical circuit can be obtained. Usually VHDL books describe both, synthesis and simulation aspects of the language, but in this book the reader is conducted just through the features acceptable by synthesis tools. The book introduces the subjects in a gradual and concise way, providing just enough information for the reader to develop their synthesizable digital systems in VHDL. The examples in the book were planned targeting an FPGA platform widely used around the world.

  • ISBN10 3319025481
  • ISBN13 9783319025483
  • Publish Date 30 November 2013 (first published 31 October 2013)
  • Publish Status Withdrawn
  • Out of Print 18 October 2014
  • Publish Country US
  • Imprint Springer
  • Format Paperback (US Trade)
  • Pages 168
  • Language English