RTL Modeling with SystemVerilog for Simulation and Synthesis: Using SystemVerilog for ASIC and FPGA Design

by Stuart Sutherland

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  • ISBN10 1546776346
  • ISBN13 9781546776345
  • Publish Date 10 June 2017
  • Publish Status Active
  • Imprint Createspace Independent Publishing Platform
  • Format Paperback (US Trade)
  • Pages 488
  • Language English