Verilog and Systemverilog Gotchas

by Professor of Experimental Psychology Stuart Sutherland and Don Mills

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This book will help engineers write better Verilog/SystemVerilog design and verification code as well as deliver digital designs to market more quickly. It shows over 100 common coding mistakes that can be made with the Verilog and SystemVerilog languages. Each example explains in detail the symptoms of the error, the languages rules that cover the error, and the correct coding style to avoid the error. The book helps digital design and verification engineers to recognize, and avoid, these common coding mistakes. Many of these errors are very subtle, and can potentially cost hours or days of lost engineering time trying to find and debug them.

  • ISBN10 038756568X
  • ISBN13 9780387565682
  • Publish Date 21 March 2011 (first published 26 June 2007)
  • Publish Status Withdrawn
  • Out of Print 18 October 2014
  • Publish Country US
  • Imprint Springer
  • Format Paperback (US Trade)
  • Pages 244
  • Language English