This book introduces a novel framework for accurately modeling the errors in nanoscale CMOS technology and developing a smooth tool flow at high-level design abstractions to estimate and mitigate the effects of errors. The book presents novel techniques for high-level fault simulation and reliability estimation as well as architecture-level and system-level fault tolerant designs. It also presents a survey of state-of-the-art problems and solutions, offering insights into reliability issues in digital design and their cross-layer countermeasures.
- ISBN13 9789811093210
- Publish Date 12 May 2018 (first published 5 July 2017)
- Publish Status Active
- Publish Country SG
- Imprint Springer Verlag, Singapore
- Edition Softcover reprint of the original 1st ed. 2018
- Format Paperback
- Pages 197
- Language English